Parallel Test Method for LSI (Large Scale Integration) Microprocessors.

Abstract

The parallel testing concept consists of connecting together the corresponding inputs and outputs of devices-under-test to perform monitored testing. Failures are detected by changes in supply current to the paralleled set and isolated by differences in individual device currents. The parallel testing concept was first presented by R. Alan Blore of the Rome Air Development Center (RADC) at the International Symposium for Testing and Failure Analysis in 1980. Originator-supplied keywords include: Accelerated lift testing, Parallel testing, Reliability, Burn-in, Large scale integration (LSI) microcircuits, Testing, Monitored testing.

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Document Details

Document Type
Technical Report
Publication Date
Feb 01, 1984
Accession Number
ADA150237

Entities

People

  • R. M. Koenig Jr

Organizations

  • McDonnell Douglas

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Complementary Metal-Oxide Semiconductors
  • Computers
  • Control Panels
  • Control Systems
  • Detection
  • Detectors
  • Electrical Measurement
  • Failure Mode And Effect Analysis
  • Hall Effect
  • Integrated Circuits
  • Life Tests
  • Measurement
  • Plastic Explosives
  • Semiconductor Devices
  • Semiconductors
  • Test And Evaluation
  • Test Methods

Fields of Study

  • Engineering

Readers

  • Electrical Engineering
  • Parallel and Distributed Computing.
  • Software Engineering

Technology Areas

  • Microelectronics
  • Microelectronics - Microelectromechanical Systems