EOS (Electrical Overstress) Protection for VLSI (Very Large Scale Integration) Devices.
Abstract
Many of the major semiconductor manufacturers have published the results of their own in-house design evaluations of new electrostatic discharge (ESD) protection networks. Several major users have published test and evaluation results on the ESD protection networks used on a wide cross-section of popular device types available today. The present work was undertaken to expand that data base and to compare the failure mechanisms which occur in devices subjected to both the human body and the charged device ESD simulation tests. The conclusions of this report are similar to those other workers. Failure mechanisms induced with the human body model are primarily electrothermal junction shorting, often associated with aluminum/silicon contacts near the bonding pads (an interlevel polysilicon layer placed between the aluminum and silicon in such contacts significantly raises the failure threshold). Layout mistakes such as closer spacing of protective network components to other junctions can cause significantly lowered failure thresholds for a pin. Interlayer oxide shorts were found to occur in some networks. The charged device test induced failures at much lower voltages but the failure mechanisms were similar in the best protective networks. In almost every case there were easily recognized reasons for increased sensitivity on one or more pins which could be fixed by minor layout changes.
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 01, 1984
- Accession Number
- ADA150333
Entities
People
- D. D. Wilson
- M. G. Rossi
- W. E. Echols
Organizations
- Martin Marietta