Automated Circuit Extraction from Mask Descriptions of MOS Networks.
Abstract
An automated circuit extractor generates an equivalent circuit description of an integrated circuit (IC) entirely from the geometric mask information. By analyzing the circuit description, IC performance can be estimated without having the IC design implemented. This thesis presents a methodology for accurate extraction of interconnection resistance, inter-nodal capacitance, ground capacitance, and transistor dimensions-circuit parameters important in characterizing in speed, noise-immunity, and static performance of designs for modern MOS technologies. Extracting each circuit parameter follows a general, numerical extraction algorithm with high accuracy. However, where possible, the general algorithms are replaced with simple techniques that do not sacrifice accuracy but execute much faster. Vital to the extraction methodology is a geometric operation that decomposes regions into domains appropriate for specialized algorithms and general algorithms.
Document Details
- Document Type
- Technical Report
- Publication Date
- Feb 01, 1984
- Accession Number
- ADA151208
Entities
People
- S. P. Mccormick
Organizations
- Massachusetts Institute of Technology