Automatic VLSI (Very Large Scale Integration) Routing Using 2-Layer Metal.
Abstract
The program minimizes the channel height of a channel. The channels must be rectangular. Also, each horizontal channel must intersect every vertical channel and vice versa. Alternate paths can be found for nets in horizontal channels when channel capacity is exceeded. Constraint loops are removed by ordering the way nets are routed or by introducing a 'dogleg'. The program produces output that is compatible with CLL (Chip Layout Language). The output from the program can be merged with CLL statements that place cells from a library on a grid to form plots or to create CIF (Caltech Intermediate Form) data to be used in making VLSI chips. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 01, 1983
- Accession Number
- ADA151718
Entities
People
- T. G. Hewitt
Organizations
- Air Force Institute of Technology