VLSI (Very Large Scale Integrated Circuits) Device Reliability Models.
Abstract
This report details a study in which the objective was to develop failure rate prediction models for VLSI, Hybrid, analog microprocessor, and VHSIC devices. A description is given of the various phases involved in reliability prediction model development, such as; literature collection/review, investigation of failure modes, failure rate data collection, statistical analysis methodologies, model factors quantification, and model validation. For VLSI, Hybrid and analog microprocessor devices, the models are given in a form which can easily be included in MIL-HDBK-217. For VHSIC devices, this effort was necessarily limited to the identification of necessary model factors (attributes) which should be included in a quantitative model acceptable for inclusion in MIL-HDBK-217. This effort was necessarily limited to the development of a qualitative reliability prediction model due to the lack of available data on VHSIC devices at the time of this study. Keywords include: VLSI, Hybrid microcircuit, Integrated circuit, Failure rate, MIL-HDBK-217, and Reliability prediction.
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 01, 1984
- Accession Number
- ADA153268
Entities
People
- D. Coit
- K. Key
- S. Flint
- W. Denson
- W. Turkowski
Organizations
- IIT Research Institute