Fault-Tolerant Computing Research
Abstract
This report provides a synopsis of research performed in fault- tolerant computing, for the first year of grant AFOSR-84-0052. Also included is a list of publications that have resulted from the research supported by this grant. Additionally, this report reviews the future direction for the continuing research under this grant. In the past year, this effort has focussed on the following problems: (1) Investigation of novel fault-tolerant processor array architectures with the potential of a high degree of defect tolerance, but having low processor and interconnect overhead associated with the fault tolerance mechanisms; (2) Development of realistic models to evaluate the yield, redundancy and performance tradeoffs for the designs. Such models would help establish the viability of these architectures, also enabling them to be compared with other designs in the literature; (3) Development of new and efficient testing strategies, and reconfiguration schemes for their structures; (4) Testable design of large size VLSI memory; and (5) Development of novel sorting networks that can be implemented on a single chip or wafer. Three journal articles were supported during the grant period: 'Synthesis of Directed Multicommodity Flow Networks,' Vol. 14, pp. 213-224 (with A. Stai); 'Fault- Tolerant Multiprocessor Link and Bus Network Architectures, IEEE Transactions on Computers, Vol. C-34, No. 1, January 1985, pp. 33-46; and 'Dynamically Restructurable Fault-Tolerant Processor Network Architectures,' IEEE transactions on Computers (to appear).
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 04, 1985
- Accession Number
- ADA154082
Entities
People
- Dillip K. Pradhan
Organizations
- University of Massachusetts Amherst