Design of a Sixteen Bit Pipelined Adder Using CMOS Bulk P-Well Technology.

Abstract

The design of a sixteen-bit pipelined adder complementary metal oxide semiconductor circuit is presented. The adder is designed to maximize throughput and to provide for testability. Tutorial material on CMOS design is also presented. Additional keywords: theses; VLSI(very large scale integration); computer aided design; NMOS(negatively doped metal oxide semiconductors); logic circuits. (Author).

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1984
Accession Number
ADA155043

Entities

People

  • W. R. Reid

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Bipolar Junction Transistors
  • Circuit Analysis
  • Circuits
  • Complementary Metal-Oxide Semiconductors
  • Computer Science
  • Computer-Aided Design
  • Computers
  • Digital Circuits
  • Fabrication
  • Integrated Circuits
  • Logic Gates
  • Materials
  • Metal Oxide Semiconductors
  • Semiconductors
  • Simulations
  • Simulators
  • Very Large Scale Integration

Readers

  • Integrated Circuit Design and Technology.
  • Parallel and Distributed Computing.

Technology Areas

  • Microelectronics