Fault Tolerant Statistical Signal Processing Algorithms for Parallel Architectures.

Abstract

We analyze the effects of hardware faults on the performance of computer-implemented signal detectors, as measured by the probability of detection and the probability of false alarm. We then use these results to design fault-tolerant detectors using hardware redundancy. Keywords include. Fault tolerance, Signal Processing, and Parallel Architecture.

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Document Details

Document Type
Technical Report
Publication Date
Jun 26, 1985
Accession Number
ADA157393

Entities

People

  • G. G. L. Meyer
  • H. L. Weinert

Organizations

  • Johns Hopkins University

Tags

Communities of Interest

  • Human Systems

DTIC Thesaurus Topics

  • Algorithms
  • Computer Science
  • Computers
  • Computing Devices
  • Contracts
  • Detection
  • Detectors
  • Electrical Engineering
  • False Alarms
  • Fault Tolerance
  • Military Research
  • Probability
  • Quality Control
  • Reliability
  • Security
  • Signal Processing
  • Warning Systems

Fields of Study

  • Engineering

Readers

  • Artificial Intelligence
  • Integrated Circuit Design and Technology.
  • Sensor Fusion and Tracking Systems.