Some Experiments in VLSI Leaf-Cell Optimization,

Abstract

This paper describes a method for local optimization of VLSI leaf cells, using the parameterized procedural layout language ALLENDE 5. Tradeoffs among delay time, power consumption, and area are illustrated. Three different implementations of the 1-bit full adder are compared: a random logic circuit, a data selector, and a PLA. The fastest random logic 1-bit full adder has a time-power product about 1/3 that of the fastest data selector, and about 1/4 that of the fastest PLA. The 4-bit parallel adder is used to illustrate the effect of loading when leaf cells are combined. (Author)

Open PDF

Document Details

Document Type
Technical Report
Publication Date
Jan 01, 1984
Accession Number
ADA157764

Entities

People

  • K. Iwano
  • K. Steiglitz

Organizations

  • Princeton University

Tags

Communities of Interest

  • Air Platforms
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Circuits
  • Computer Science
  • Diffusion
  • Digital Signal Processing
  • Electrical Engineering
  • Engineering
  • Integrated Circuits
  • Inverters
  • Language
  • Logic
  • Logic Gates
  • Military Research
  • Nand Gates
  • Optimization
  • Signal Processing
  • Topology
  • Very Large Scale Integration

Readers

  • Computer Programming and Software Development.
  • Integrated Circuit Design and Technology.
  • Operations Research