Bulk CMOS VLSI Technology Studies. Part 1. Scalable CMOS Design Rules. Part 2. CMOS Approaches to PLA (Programmable Logic Array) Design.

Abstract

Part 1: Scalable CMOS design rules are developed for the MOSIS community to facilitate fabrication from a single design at 3 microns and 1.3 microns VHSIC dimensions. Part 2: Various Programmable Logic Array (PLA) implementations with clocked CMOS technology are explored in this project. Three different CMOS PLA circuit styles are described: the large PLA uses a gated OR plane and is useful for a system with large number of inputs; the moderate PLA and the small PLA are ripple varieties with the former having the capability of handling a larger number of inputs than the latter. Path Programmable Logic (PPL), which is a folded form of a PLA, is also studied. A symbolic form of representation is developed and future PPL development activities are discussed. The PPL approach has a size and flexibility advantage over the other PLA approaches - except in applications requiring large PLA's.

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Document Details

Document Type
Technical Report
Publication Date
Jun 17, 1985
Accession Number
ADA158367

Entities

People

  • A. K. R. Naini
  • J. D. Trotter

Organizations

  • Mississippi State University

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Circuits
  • Classification
  • Computer Programming
  • Computers
  • Contracts
  • Databases
  • Electrical Engineering
  • Engineering
  • Fabrication
  • Integrated Circuits
  • Logic
  • Logic Devices
  • Logic Gates
  • Military Research
  • Nand Gates
  • Standards
  • Storage

Fields of Study

  • Physics

Readers

  • Asian Economic Studies
  • Integrated Circuit Design and Technology.