VLSI (Very Large Scale Integrated) Design of a Sixteen Bit Pipelined Multiplier Using three Micron NMOS Technology.

Abstract

The application of computer-aided design (CAD) tools in the full custom design and testing of a 16-bit pipelined two's complement multiplier in three micron NMOS is described. A comparison between the full custom carry-save addition (CSA) multiplier designed using CAD tools and a multiplier generated by the MacPitts silicon compiler is presented. Additional background material is also presented on the CSA multiplication algorithm used. Keywords: NMOS VLSI design; Pipelined multiplier; Two's complement multiplier; CAD tools; MacPitts silicon compiler; VLSI(Very Large Scale Integration); Integrated Circuits(Theses).

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Document Details

Document Type
Technical Report
Publication Date
Jun 01, 1985
Accession Number
ADA159433

Entities

People

  • R. J. Simchik Jr

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Circuits
  • Computer Science
  • Computer-Aided Design
  • Computers
  • Diagrams
  • Electrical Engineering
  • Energy Consumption
  • Engineering
  • Equations
  • Fabrication
  • Integrated Circuits
  • Nand Gates
  • Operating Systems
  • Simulations
  • Simulators
  • United States
  • Very Large Scale Integration

Fields of Study

  • Engineering

Readers

  • Computer Engineering
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