Investigation of High Speed ICs in InP Using MIS Structures.

Abstract

A 3x3 digital multiplier IC has been developed using InP MISFET technology. A modified enhancement/depletion circuit approach with source follower input transistors was selected for use on the basis of being tolerant to process variations. In a self test mode of the multiplier, multiply times of 11 ns were observed. Keywords include: Indium phosphide; Integrated circuits (ICs); Semi Insulating; Logic circuits; MISFETs; Digital multipliers; High speed circuits; InP process technology; and InP Integrated Circuits.

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Document Details

Document Type
Technical Report
Publication Date
Oct 01, 1984
Accession Number
ADA159652

Entities

People

  • D. K. Kinell

Organizations

  • Lockheed Martin Missiles and Space

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Chemical Vapor Deposition
  • Circuit Analysis
  • Circuits
  • Diagrams
  • Electrical Engineering
  • Fabrication
  • Frequency
  • Integrated Circuits
  • Logic
  • Logic Gates
  • Materials
  • Military Research
  • Nand Gates
  • Power Supplies
  • Semiconductors
  • Test Equipment
  • Waveforms

Readers

  • Integrated Circuit Design and Technology.
  • Semiconductor Device Technology

Technology Areas

  • Microelectronics