A Systolic Array Implementation of a Reed-Solomon Encoder and Decoder.

Abstract

A systolic array is a natural architecture for the implementation of a Reed-Solomon (RS) encoder and decoder. It possesses many of the properties desired for a special-purpose application: simple and regular design, concurrency, modular expansibility, fast response time, cost-effectiveness, and high reliability. As a result, it is very will suited for the simple and regular design essential for VLSI implementation. This thesis takes a modular approach to the design of a systolic array based RS encoder and decoder. Initially, the concept of systolic arrays is discussed followed by an introduction to finite field theory and Reed-Solomon error correction codes. Then it is shown how RS codes can be encoded and decoded with primitive shift registers and implemented using a systolic architecture. In this way, the reader can gain valuable insight and comprehension into how these entities are coalesced together to produced the overall implementation. Additional keywords: Systolic multipliers. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Jun 01, 1985
Accession Number
ADA159824

Entities

People

  • S. S. Mckenzie

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Energy and Power Technologies
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Coders
  • Communication Channels
  • Computations
  • Computer Programming
  • Computer Science
  • Computers
  • Data Transmission
  • Detection
  • Digital Communications
  • Electrical Engineering
  • Error Correction Codes
  • Numbers
  • Parallel Computing
  • Parallel Processing
  • Parallel Processors
  • Processing Equipment
  • United States

Fields of Study

  • Engineering

Readers

  • Parallel and Distributed Computing.
  • Radio communications and signal processing.
  • Systems Analysis and Design