Area Estimation of VLSI Integrated Circuits.

Abstract

In this report, we present the problem of estimating the area of digital integrated circuits. This problem is important for reasons of chip yield, floor planning and design turnaround time. Area estimation is to be done at different levels of hierarchy. A model is presented for estimating the dimensions of the random logic blocks of a chip, given the description of these blocks as their constituent cells and their interconnections. We will pursue this research towards building a complete area estimation system which can handle different layout methodologies, can perform estimation at higher levels of design description (namely the Register-Transfer level), and be a useful aid to floorplanning and total layout as part of the ADAM system.

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Document Details

Document Type
Technical Report
Publication Date
Jul 24, 1985
Accession Number
ADA160335

Entities

People

  • A. C. Parker
  • F. J. Kurdahi

Organizations

  • University of Southern California

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Algorithms
  • Aspect Ratio
  • Circuit Boards
  • Computational Science
  • Computer Programming
  • Computer-Aided Design
  • Computers
  • Electrical Engineering
  • Estimators
  • Integrated Circuits
  • Printed Circuits
  • Probabilistic Models
  • Probability
  • Random Variables
  • Simulations
  • Standards
  • Two Dimensional

Fields of Study

  • Engineering

Readers

  • Computational Modeling and Simulation
  • Integrated Circuit Design and Technology.