Low Power, Radiation Hard GaAs RAM
Abstract
The scope of this program is to demonstrate a 1K GaAs static RAM having very low power dissipation and short access time to meet the requirements of the DARPA Advanced On-Board Signal Processer (AOSP). Device isolation and backgating studies were performed, subthreshold uniformity measurements made, and a new RAM design using transmission gates finalized. Proton damage has proven to be an effective technique for maximizing device isolation for ultra- low power RAM circuits. However, backgating still remains as a possible yield limiting factor. Backgating measurements have been performed on test structures to determine the influence of backgating in proton isolated material with differing acceptor content. The results have been used to refine models for backgating and to identify properties of the starting GaAs material which affect backgating and isolation. A technique to characterize FET devices within a RAM has been successfully developed. It applies to test arrays of 224 (16 x 14) RAM cells extracted from the 1K RAM, and which have each row word-line, and each column bit-sense line connected to a contact pad. With a proper biasing scheme, and using our parametric test system, the subthreshold characteristic of the output FET in each of the 72 cells forming the central core of the array can be measured individually. The device characteristics appear uniform and well behaved, as expected from measurements on single devices. The design of a transmission gate RAM has been completed and will be implemented on the RM5 mask set.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 01, 1985
- Accession Number
- ADA161160
Entities
People
- E. Walton
- K. Elliot
- R. Vahrenkamp
- R. Zucca