A Performance Analysis of Multiprocessors Using Two-Level Caches.

Abstract

This thesis proposes a two-level cache organization for multiprocessors. The first level of cache consists of a private cache per processor. The second level of caches is shared by all processors. The main memory is also similarly shared. A cache coherence solution is proposed for such an organization. The performance of the proposed multi-processor is evaluated with analytical methods. The factors that affect the performance are quantitatively discussed. A variation of the proposed coherence algorithm is presented to improve the performance. Keywords: High reliability; Cache memories; Mathematical analysis. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Aug 01, 1984
Accession Number
ADA161552

Entities

People

  • Daniel James Colglazier

Organizations

  • University of Illinois Urbana–Champaign

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  • Materials and Manufacturing Processes

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  • Computer Architecture
  • Computers
  • Computing System Architectures
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  • Data Transmission
  • Illinois
  • Instruction Set Architecture
  • Mathematical Analysis
  • Multiprocessors
  • Numerical Analysis
  • Operating Systems
  • Parallel Processing
  • Security
  • United States
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  • Computational Modeling and Simulation
  • Parallel and Distributed Computing.