Functional Testing of LSI/VLSI Based Systems with Measure of Fault Coverage.

Abstract

The author has studied thoroughly the fundamental contributions made by Thatte and Abraham who have considered the problem of micro-processor testing, Based on the architecture information available to a user and the instruction set for a given microprocessor, they define a graph model of the microprocessor under consideration. This model is then used to derive necessary tests. Their approach is, first to label the nodes and edges in the graph based on the observability of such nodes and edges. The faults are divided into five different classes namely register decoding, instruction decoding/control, data path, data storage and data manipulation faults. Explicit models are given for all these fault classes and functional units. It is assumed that no more than one functional unit is faulty, though any number of faults of one class can be present. Procedures are then developed to detect faults of different classes. They have also studied the fault coverage of their tests for a Hewlett Packard system.

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Document Details

Document Type
Technical Report
Publication Date
Nov 05, 1982
Accession Number
ADA161927

Entities

People

  • Stephen Y. H. Su

Organizations

  • State University of New York at Albany

Tags

DTIC Thesaurus Topics

  • Circuits
  • Computing System Architectures
  • Data Storage Systems
  • Decoding
  • Demographic Cohorts
  • Instruction Set Architecture
  • Instructions
  • Language
  • Microprocessors
  • New York
  • Sequences
  • Short Circuits
  • Test Methods
  • Test Sets
  • Universities

Fields of Study

  • Engineering

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