Interprocessor Communication Issues in Fat-Tree Architectures,
Abstract
In recent years, it has become increasingly evident that conventional computer architectures will be unable to perform, in an acceptable time frame, many of the computational functions that we would desire of them. Consequently, much research has been devoted to the concept of constructing super-computers, which will be able to exploit the potential for parallel computation intrinsic to many large computational problems. Recently, Leiserson has proposed a multiprocessor scheme based on Leighton's tree of meshes, called a fat-tree. Conceptually, such a multiprocessor would be comprised of a set of n processing elements each situated as a leaf in a complete binary tree. Internal modes would be high speed switches which route messages being passed between processing elements, while edges between nodes would be bundles of constant bandwidth communication paths. The purpose of this document will be to address and define some of the issues which effect interprocessor communication within a fat-tree multiprocessor. Specifically, it covers the following topics: (1) Addressing in a fat-tree; (2) Generation of addresses in a fat-tree; and (3) Allocation of communication resources in a fat-tree.
Document Details
- Document Type
- Technical Report
- Publication Date
- Oct 01, 1985
- Accession Number
- ADA163425
Entities
People
- Alexander Toichi Ishii
Organizations
- Massachusetts Institute of Technology