Microprocessor Controller With Nonvolatile Memory Implementation.
Abstract
In support of the Naval Postgraduate School's space program, a small, self-sufficient, low power microprocessor controller with nonvolatile memory has been designed, constructed and tested. Because of limited battery power availability, Complementary Metal-Oxide Semiconductor components have been used. The controller uses the National semiconductor NSC800 CPU along with three NSC810A RAM-I/O-Timers. Other features include a 16 channel analog-to-digital converter, a real time clock, local memory in the form of EPROM and RAM, and the Intel BPK 72 Bubble Memory System. The general nature of the controller allows it to be reprogrammed and utilized in a variety of applications. Prior thesis research by Captain Mike Snyder, U.S. Army, using the NSC888 Self-Contained NSC800 Evaluation System Ref. 1 has been expanded upon in this thesis project. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 01, 1985
- Accession Number
- ADA164152
Entities
People
- Jay W. Wallin
Organizations
- Naval Postgraduate School