Synthesis of High-Speed Digital Systems.
Abstract
The design of high-speed systems and the automation of the design tasks involved is the topic of this thesis. In particular, the focus is on the use of pipelining and general overlapped execution in order to speed up the systems being implemented. This thesis contains new techniques for speed-up, and describes the implementation of these techniques in a set of design automation programs. The new techniques produce designs which share resources and time in a manner which is more complex that used as common practice in working systems. The manual design of such complex hardware would be virtually impossible; thus, automated design is a key aspect of the proposed design methodology. The specific problem the thesis addresses is the following: the determination of the point in time each operation in a set of tasks is to be performed, and the manner in which the operators which execute each operation are reused from cycle to cycle. Three topics are investigated: 1) clocking scheme synthesis; 2) synthesis of pipelined data paths; and, 3) the insertion of delays into pipelined systems to avoid resources conflicts while increasing performance.
Document Details
- Document Type
- Technical Report
- Publication Date
- Nov 08, 1985
- Accession Number
- ADA164690
Entities
People
- Nohbyung Park
Organizations
- University of Southern California