A Coherent VLSI Design Environment.
Abstract
This report covers the period from October 1, 1985 through March 31, 1986. The research discussed here is described in more detail in several published and unpublished reports cited below. The CAD frame Schema has received limited but instructive applications. Connections to remote simulation servers are transparent to the user. More substantial uses are anticipated during the next half year. Waveform bounding results have been extended to ECL technology, and a variety of the results are being applied to an analog application in early vision. Many of the previous results have been transferred to industry and are bing used in commercial simulators. Fundamental speed limits of collections of active devices with parasitics have been found. These are independent of how the devices are interconnected. A reliability simulator has been written, and models are being developed for it, to describe three important effects, namely mental migration, hot-electron trapping, and time-dependent dielectric breakdown. Work continues on the fat-tree architecture, and on the efficient realization of various classes of circuits. New results in graph bisection and routing were made during this period. It is now known how to imbed some classes of communications networks in others, for example binary trees in hypercubes. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 31, 1986
- Accession Number
- ADA166848
Entities
People
- Paul Penfield Jr.
Organizations
- Massachusetts Institute of Technology