Hardware Implementation of a Concatenated Encoder/Decoder.

Abstract

This study describes the hardware implementation of a concatenated error correcting encoder/decoder. Individual burst and random error correcting coders were implemented using standard TTL integrated circuits and Z-80 microprocessors. The circuits handle input and output operations with a three line handshake. Thus, data transfer between circuits is asynchronous, and the coders may be concatenated in any order. Reed-Solomon, BCH, Golay, interleaving, and convolutional codes were considered. Of these codes, the BCH encoder/decoder, the Golay encoder/decoder, the interleaver/deinterleaver, and the convolutional encoder were all implemented in hardware. The Reed-Solomon encoder/decoder and the convolutional decoder will be implemented in a follow-on study in software. This study is the first part of a group of studies which will ultimately determine the actual error detection and correction performance of various concatenated coding schemes. Keywords: Computer programs; Assembly language. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1985
Accession Number
ADA167069

Entities

People

  • Peter W. De Graaf

Organizations

  • Air Force Institute of Technology

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Assembly Languages
  • Circuits
  • Coding
  • Communication Systems
  • Computer Programming
  • Computer Programs
  • Computers
  • Data Transmission
  • Decoding
  • Detection
  • Digital Communications
  • Electrical Engineering
  • Engineering
  • Language
  • Microprocessors
  • Security
  • Test And Evaluation

Fields of Study

  • Engineering

Readers

  • Computer Programming and Software Development.
  • Software Engineering