The RISC (Reduced Instruction Set Computer) Architecture and Computer Performance Evaluation.

Abstract

A definition of Reduced Instruction Set Computers is developed. A computer performance model which allows the evaluation of architectural alternatives is presented. An example on the use of the model to compute the performance altenatives for a given application is presented to study the effect of the addition of an instruction to a processor instruction set. Keywords: Theses; Minicomputers). (Author)

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Document Details

Document Type
Technical Report
Publication Date
Mar 01, 1986
Accession Number
ADA167873

Entities

People

  • Manuel F. P. De Barros

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • C4I

DTIC Thesaurus Topics

  • Access Time
  • Application Software
  • Computer Architecture
  • Computer Components
  • Computer Programs
  • Computers
  • Computing System Architectures
  • Fast Fourier Transforms
  • Instruction Set Architecture
  • Instructions
  • Life Cycles
  • Measurement
  • Midrange Computers
  • Operating Systems
  • Parallel Computing
  • Parallel Processing
  • Test And Evaluation

Readers

  • Parallel and Distributed Computing.