Delay Modeling of Bipolar ECL/EFL (Emitter-Coupled Logic/Emitter-Follower-Logic) Circuits.

Abstract

This report deals with the development of a delay-time model for timing simulation of large circuits consisting of Bipolar ECL(Emitter-Coupled Logic) and EFL (Emitter-Follower-Logic) networks. This model can provide adequate information on the performance of the circuits with a minimum expenditure of computation time. This goal is achieved by the use of proper circuit transient models on which analytical delay expressions can be derived with accurate results. The delay-model developed in this report is general enough to handle complex digital circuits with multiple inputs or/and multiple levels. The important effects of input slew rate are also included in the model. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Aug 01, 1986
Accession Number
ADA171131

Entities

People

  • Andrew T. Yang

Organizations

  • University of Illinois Urbana–Champaign

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Bipolar Junction Transistors
  • Circuit Analysis
  • Circuits
  • Computations
  • Computer-Aided Design
  • Computers
  • Digital Circuits
  • Engineering
  • Illinois
  • Logic Gates
  • P-N Junctions
  • Semiconductors
  • Simulations
  • Simulators
  • Steady State
  • Universities
  • Valence Bond Theory

Readers

  • Computational Modeling and Simulation
  • Integrated Circuit Design and Technology.