Charge Sharing Models for MOS Circuits.

Abstract

This paper addresses timing and glitch detection problems involving charge sharing in acyclic resistor capacitor networks. Solutions to these problems are proposed and applied to real designs. Results are reported and compared with SPICE simulation. Our algorithms are intended for use in switch level simulators and timing verifiers which model transistors in digital VLSI designs as linear resistors. Computational complexity of our methods is also investigated. (Author)

Document Details

Document Type
Technical Report
Publication Date
Jan 01, 1983
Accession Number
ADA177695

Entities

People

  • Chorng-yeong Chu
  • Mark A. Horowitz

Organizations

  • Stanford University

Tags

DTIC Thesaurus Topics

  • Algorithms
  • Capacitors
  • Computational Complexity
  • Detection
  • Electronic Components
  • Electronic Equipment
  • Mathematics
  • Passive Electronic Components
  • Resistors
  • Simulations
  • Simulators
  • Transistors

Readers

  • Integrated Circuit Design and Technology.
  • Parallel and Distributed Computing.