A Single Chip LSI High-Speed Functional Tester,
Abstract
A new architecture of single chip tester, DGR, will be proposed. It generates test vectors designated by the internal memory data, and simultaneously, detects the DUT data, being overwritten on that memory. A prototype chip designed by 3um CMOS contains 64.5K transistors in a die size of 9.2mm by 7.9mm, and dissipates less than 300mW at an operating frequency of 10MHz.
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 16, 1986
- Accession Number
- ADA177886
Entities
People
- Jun-ichi Miyamoto
- Mark A. Horowitz
Organizations
- Stanford University