A 20 MIPS Peak Microprocessor with On-Chip Cache,

Abstract

MIPS-X is a 32b microprocessor with an on-chip 16Kb instruction cache. The chip is implemented in a 2 micron drawn channel length, 2-layer metal CMOS technology, contains 150K transistors in an 8mm by 8.5mm die, and has 84 signal pins and 24 power pins. At a peak operating frequency of 20MHz the chip will dissipate less than 2W. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Jan 01, 1984
Accession Number
ADA177929

Entities

People

  • John L. Hennessy
  • John M. Acken
  • Mark Horowitz
  • P. G. Gulak
  • Paul Chow

Organizations

  • Stanford University

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Bandwidth
  • Contracts
  • Displacement
  • Engineering
  • Fabrication
  • Frequency
  • Instructions
  • Integrated Systems
  • Microprocessors
  • Pipelines
  • Simulations
  • Throughput
  • Transistors
  • Universities

Readers

  • Integrated Circuit Design and Technology.
  • Mathematics or Statistics
  • Parallel and Distributed Computing.