A VLSI CMOS Circuit Design Technique to Aid Test Generation,

Abstract

This paper describes a new design technique for fully-testable CMOS combinational circuits and a 3-pattern test scheme to detect switch-level (stuck-open and stuck-on) faults. A fully-testable combinational circuit is implemented with specially designed gates that have no undetectable stuck-on faults. Switch-level faults in this type of combinational circuit can be detected with a 3-pattern test scheme. These 3-pattern tests are easy to generate with a gate-level automatic test pattern generator (ATPG) that offers better performance than a switch-level ATPG.

Document Details

Document Type
Technical Report
Publication Date
Jan 01, 1986
Accession Number
ADA177934

Entities

People

  • Dick L. Liu
  • Edward J. Mccluskey

Organizations

  • Stanford University

Tags

DTIC Thesaurus Topics

  • Automatic
  • Demographic Cohorts
  • Demography
  • Energy Systems
  • Generators

Fields of Study

  • Engineering

Readers

  • Applied Combinatorial Optimization and Logic Circuit Design.
  • Integrated Circuit Design and Technology.