The MIPS-X Microprocessor,

Abstract

MIPS-X is the successor to the MIPS project at Stanford University. Like its predecessor, it is a single chip VLSI processor that uses a simplified instruction set, pipelining and a software code reorganizer to obtain high performance. Key features include single cycle execution of all instructions, use of an on-chip 512-word instruction cache, coprocessor support, and support for multiprocessor operation. The processor is being designed in a 2 micron, 2-level metal CMOS technology, and should have a cycle time of 50 ns.

Document Details

Document Type
Technical Report
Publication Date
Jan 01, 1985
Accession Number
ADA178009

Entities

People

  • Mark Horowitz
  • Paul Chow

Organizations

  • Stanford University

Tags

DTIC Thesaurus Topics

  • Instruction Set Architecture
  • Instructions
  • Microprocessors
  • Multiprocessors
  • Processing Equipment
  • Universities

Readers

  • Parallel and Distributed Computing.