A Hyperconcentrator Switch for Routing Bit-Serial Messages.

Abstract

In highly parallel message routing networks, it is sometimes desirable to concentrate relatively few messages on many wires onto fewer wires. We have designed a VLSI chip for this purpose which is capable of concentrating bit-serial messages quickly. This hyperconcerntrator switch has a highly regular layout using ratioed nMOS and takes advantage of the relatively fast performance of large fan-in NOR gates in this technology. A signal incurs exactly 21gn gate delays through the switch, where n is the number of inputs to the circuit. The architecture generalizes to domino CMOS as well. Keywords include: Message routing network, bit-serial message, concentrator switch, hyperconcentrator switch, superconcentrator switch butterfly network, merge sort, and VLSI.

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Document Details

Document Type
Technical Report
Publication Date
Feb 01, 1987
Accession Number
ADA178402

Entities

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  • Charles E. Leiserson
  • Thomas H. Cormen

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  • Massachusetts Institute of Technology

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