Design of Fault Tolerant Prime Factor Algorithm Array Elements.

Abstract

The calculation of the discrete Fourier transform (DFT) has long been a significant bottleneck in many Digital Signal Processing applications. This thesis contributes to the goal of implementing a very large-scale integrated (VLSI) circuit which uses the Winograd and Good-Thomas algorithms for computing DFTs with composite blocklengths. Winograd processors use both the small and large Winograd algorithms to compute DFTs with blocklengths of 15, 16, and 17. Longer blocklength DFTs (240, 255, 272, and 4080 are computed using a pipeline of Winograd processors, dual-port memories, and a controller. The pipeline used the Good-Thomas Prime Factor Algorithm. Fault tolerance was enhanced by the use of watchdog processors to provide concurrent fault detection and error control coding to provide fault masking. A pipeline controller was designed as a Reduced Instruction Set Computer to control the pipeline and regulated the flow of data. Also, a dual ported, double buffered RAM memory was designed to provide intra-pipeline data storage. Keywords: Theses; Algorithms; Computer Architecture.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1986
Accession Number
ADA178977

Entities

People

  • Gary D. Hedrick

Organizations

  • Air Force Institute of Technology

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Air Force
  • Coding
  • Computer Programming
  • Computers
  • Computing System Architectures
  • Data Storage Systems
  • Decoding
  • Detection
  • Digital Signal Processing
  • Discrete Fourier Transforms
  • Electrical Engineering
  • Fault Tolerance
  • Instruction Set Architecture
  • Integrated Circuits
  • Logic Gates
  • Signal Processing
  • Very Large Scale Integration

Fields of Study

  • Engineering

Readers

  • Computer Programming and Software Development.
  • Integrated Circuit Design and Technology.