A New Multi-Decoder PLA Design.

Abstract

A multi-decoder design for Programmable Logic Array devices is introduced and found to be both two decoder ROM and single decoder PLA devices in implementing a special class of Boolean expressions. In this class, the logic expressions may be lengthy but are restricted in the number of input variables comprising each p-term. A theoretical analysis of the area efficiency of the new design is supplemented by CAD design examples which verify its superiority. Implementation of the multi-decoder design using three dimensional microcircuit topography to attain even greater savings in area and speed is considered in the conclusion of this report.

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Document Details

Document Type
Technical Report
Publication Date
Mar 01, 1987
Accession Number
ADA180092

Entities

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  • Adly T. Fan
  • Mark T. Pronobis
  • Mathew R. Vitallo

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  • University at Buffalo

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  • Microelectronics