MIPS-X Instruction Set and Programmer's Manual.

Abstract

This manual describes the visible architecture of the MIPS-X processor and the timing information required to execute correct programs. MIPS-X is a pipelined processor that has no hardware interlocks. Therefore, the software system is responsible for keeping track of the timing of the instructions. The processor has a load/store architecture and supports a very small number of instructions. The instruction set of the processor will be described. The processor supports two types of coprocessor interfaces. One interface is dedicated to the floating point unit and the other will support up to 7 other compressors. These instructions will also be described.

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Document Details

Document Type
Technical Report
Publication Date
May 01, 1986
Accession Number
ADA181619

Entities

People

  • Paul Chow

Organizations

  • Stanford University

Tags

DTIC Thesaurus Topics

  • Algorithms
  • Arithmetic
  • Assembly Languages
  • Coding
  • Computations
  • Computer Programming
  • Computer Science
  • Computers
  • Computing System Architectures
  • Directives
  • Displacement
  • Electrical Engineering
  • Floating Point Operations
  • Instruction Set Architecture
  • Instructions
  • Notation
  • Precision

Readers

  • Computer Science/Computer Engineering/Data Science/Digital Signal Processing.
  • Parallel and Distributed Computing.