A Static RAM as a Fault Model Evaluator,

Abstract

This investigation considers the relationship between the physical failures that occur during fabrication and the resulting faulty behavior of the circuit. Fault models are used to describe the operation of integrated circuits containing physical failures introduced during fabrication. The effectiveness of fault models is dependent upon both the accuracy of the model and the occurrence of the underlying failure mechanism. A specially designed static RAM provides the size, design style, and testability required of a fault model test bed. An actual RAM implementation is described which was used for evaluation of fault models.

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Document Details

Document Type
Technical Report
Publication Date
Jan 01, 1987
Accession Number
ADA182300

Entities

People

  • John M. Acken
  • Mark Horowitz

Organizations

  • Stanford University

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Accuracy
  • Amplifiers
  • Circuits
  • Complementary Metal-Oxide Semiconductors
  • Diagrams
  • Fabrication
  • Failure Analysis
  • Failure Mode And Effect Analysis
  • Integrated Circuits
  • Logic
  • Model Tests
  • Power Supplies
  • Semiconductor Manufacturing
  • Simulations
  • Test And Evaluation
  • Test Beds
  • Test Vehicles

Fields of Study

  • Engineering

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