Built-in-Test Verification Techniques
Abstract
This report documents the effort to develop practical verification methodologies for the accurate and economical test and demonstration of Built-In-Test (BIT) subsystems and circuitry. These methodologies are to be applicable to both formal verification of a system for demonstration of BIT effectiveness (test system verification), and under operational conditions, to verify that the BIT is functioning as designed (test system condition assessment). Currently BIT is verified by analysis of the design or by demonstration of limit set of simulated faults. Verification of BIT capability by design analysis for verification purposes is not currently recognized as a reliable means of verification. Use of simulated set of faults has also proven to have low effectiveness for evaluation of BIT capabilities, as well as being costly. BIT on equipment in the field can seldom be tested to discover failures in the BIT circuitry, which results in gradual degradation of BIT effectiveness. Keywords include: Built-In-Test, BIT, BIT Verification, Built-In-Test Verification, Simulation, and Verification.
Document Details
- Document Type
- Technical Report
- Publication Date
- Feb 01, 1987
- Accession Number
- ADA182335
Entities
People
- Jeffrey H. Albert
- Mike J. Partridge
- Richard J. Spillman
Organizations
- Boeing