Generating Incremental VLSI Compaction Spacing Constraints,
Abstract
This paper describes using adjacency lists to incrementally generate design rule spacing constraints. The algorithm generates the smallest complete set of constraints for a design, yielding fast compaction, and is as fast or faster than ordinary constraint generation methods even when the incremental features are not used. The adjacency list data structure allows one to very quickly move, insert or delete objects and generate an updated set of constraints.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 01, 1986
- Accession Number
- ADA182460
Entities
People
- Clyde W. Carpenter
- Mark Horowitz
Organizations
- Stanford University