An Experiment on Intermittent-Failure Mechanisms.

Abstract

Intermittent failures are studied by stressing (temperature, supply voltage and extra loading) good parts. The behavior of the chips under stress is similar to that of a marginal chip under normal operating conditions. The experiments show that most intermittent failures are pattern-sensitive for both sequential and combinational circuits. The stuck-at fault model is shown to be inappropriate to describe intermittent failures. This paper presents a case where a single intermittent failure is not detected by a test set with 100% single stuck-at fault coverage. A stress-strength analysis is presented to explain the experimental results. Keywords: Intermittent failures, Pattern sensitive faults, Soft failures, Integrated circuit reliability, Intermittent fault model.

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Document Details

Document Type
Technical Report
Publication Date
Mar 01, 1987
Accession Number
ADA183572

Entities

People

  • Edward J. Mccluskey
  • Mario L. Cortes

Organizations

  • Stanford University

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Circuit Analysis
  • Computers
  • Contracts
  • Digital Circuits
  • Electrical Engineering
  • Engineering
  • Engineers
  • Failure Mode And Effect Analysis
  • High Temperature
  • Integrated Circuits
  • Logic
  • Logic Gates
  • Low Voltage
  • Military Research
  • Nand Gates
  • Semiconductors
  • Xor Gates

Fields of Study

  • Engineering

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