Specification and Design Methodologies for High-Speed Fault-Tolerant Array Algorithms and Structures for VLSI.

Abstract

For convenience we summarize here the project objectives as stated in the research proposal. This research in the methodologies for the specification and design of high-speed, fault-tolerant VLSI array structures has two related objectives (1) a high-level language approach to the specification and simulation of VLSI algorithms and networks using a functional-style (LISP-like) language (Task 1), and (2) cost-effective methods to introduce fault-tolerance (error detection, fault location, retry, and reconfiguration) into VLSI-implemented systolic systems and similar computing arrays (Task 2).

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Document Details

Document Type
Technical Report
Publication Date
Jun 01, 1987
Accession Number
ADA183772

Entities

People

  • Algirdas Avizienis
  • Miloes D. Ercegovac
  • Tomas Lang

Organizations

  • University of California, Los Angeles

Tags

Communities of Interest

  • Advanced Electronics
  • C4I
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Algorithms
  • Circuits
  • Computations
  • Computer Programming
  • Computer Science
  • Computers
  • Detection
  • Fault Tolerance
  • Geometry
  • High Level Languages
  • Language
  • Networks
  • Programming Languages
  • Simulations
  • Topology
  • Two Dimensional
  • Very Large Scale Integration

Fields of Study

  • Engineering

Readers

  • Parallel and Distributed Computing.
  • Systems Analysis and Design