Fault-Tolerant Multiprocessor and VLSI-Based Systems.
Abstract
Study and development of certain fault-tolerant architectures that utilize the capabilities of new IC technology was undertaken. Specifically, the research was aimed at network architectures, distinguished by a close interconnection of a large number of computing elements. Included is a subclass of specialized network architectures known as VLSI processor arrays. Besides fault-tolerance-related research for such arrays, also proposed was exploration of a new array architecture, developed for the express purpose of executing general algorithms on these arrays. The precise research formulated-developing fault-tolerant multiprocessor network architectures-goes beyond earlier work. Here, the system interconnection structure, itself, was used as the primary design tool for achieving various and diverse objectives, including: low interconnection and layout complexities, dynamic reconfigurability, fault-tolerance through graceful degradation as well as self-diagnosability. Viability of the proposed research was demonstrated in the proposal; new communication structures were introduced, along with concepts of admissability of multiple logical configurations, and algorithmic and detour routing that provide fault-tolerance and graceful degradation.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 15, 1987
- Accession Number
- ADA183820
Entities
People
- Dhiraj K. Pradhan
Organizations
- University of Massachusetts Amherst