An Extension to the Multilevel Logic Simulator for Microcomputers.

Abstract

One of the most time consuming parts of the design process is the debugging of the project. This happens when simple modifications to a circuit require recompilation of the whole circuit. In the CAD tool currently available for digital systems design, compilation is a bottle neck. The VOHL system has an extremely efficient simulator phase and a reasonable but slower compilation phase. This thesis investigates a mechanism for eliminating the need to recompile the complete circuit when small changes are needed.

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Document Details

Document Type
Technical Report
Publication Date
Jun 01, 1987
Accession Number
ADA185032

Entities

People

  • Julio C. De Albuquerque

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Advanced Electronics
  • C4I
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Classification
  • Compilers
  • Computer Programs
  • Computers
  • Debugging
  • Delay
  • Digital Circuits
  • Electrical Engineering
  • Engineering
  • Hash Tables
  • Industrial Engineering
  • Personal Computers
  • Simulations
  • Simulators
  • Standards
  • Systems Engineering
  • Three Dimensional

Fields of Study

  • Physics

Readers

  • Parallel and Distributed Computing.