Expanded VLSI Architectures.

Abstract

This paper describes a non von Neumann architecture which also conforms to the requirements for VLSI implementation - expanded VLSI architectures. In expanded VLSI machines, more than O(n) processors are used to solve O(n) problems, where inexpensive (in terms of silicon area), fast processors have been added to simplify the processor interconnections. Expanded architectures are constructed by deriving algorithms which trade many of one type of operation, like addition, for regularity of data movement. An expanded architecture for the Discrete Fourier Transform problem is derived. Three operational components are described, each of which can be implemented in one (or a few) VLSI chips. Optimal measures for silicon area and processing time are primary concerns. (Author)

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Document Details

Document Type
Technical Report
Publication Date
Sep 01, 1984
Accession Number
ADA185105

Entities

People

  • Mary J. Irwin
  • Robert M. Owens

Organizations

  • Pennsylvania State University

Tags

Communities of Interest

  • Advanced Electronics
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Algorithms
  • Arithmetic
  • Computations
  • Computer Architecture
  • Computer Science
  • Computers
  • Computing System Architectures
  • Discrete Fourier Transforms
  • Mathematics
  • Military Research
  • Numbers
  • Precision
  • Square Roots
  • Universities

Fields of Study

  • Engineering

Readers

  • Computer Science.
  • Graph Algorithms and Convex Optimization.
  • Integrated Circuit Design and Technology.