Prolog for VLSI Layout: Experiences in the Design and Implementation of Topolog, A Prolog Based Module Generation and Layout System
Abstract
The Topolog module generator is the major circuit-design component of the ASP silicon compiler. Topolog is an attempt to determine the utility of Prolog specifically and logic programming generally for the programming of solutions to large-scale VLSI circuit design problems. We have verified that Prolog's clause-based programming style permits easy extensibility of VLSI module generators for new technologies and user-written macroblocks. We have demonstrated that Prolog, even without the well-known assert, retract, and write operators is not a pure applicative language. We have devised a method of type definition in Prolog, and have preliminary evidence that our method is superior in efficiency to the general term unification method commonly found in the literature. (Author)
Document Details
- Document Type
- Technical Report
- Publication Date
- Jul 01, 1987
- Accession Number
- ADA185139
Entities
People
- Alvin M. Despain
- Gino Cheng
- Patrick C. Mcgeer
- William R. Bush
Organizations
- University of California, Berkeley