Ion Implanted GaAs IC (Integrated Circuit) Process Technology
Abstract
This report covers the sixth quarter, Phase II of a program on ion implanted planar GaAs integrated circuit technology. The bulk of the work on this program is carried out at the Rockwell International Electronics Research Center (ERC). Significant assistance is provided by three subcontractors; Crystal Specialties Inc. in crystal growth, California Institute of Technology in ion implantation and related materials technologies, and Cornell University in device modeling. With MSI circuit complexity well demonstrated, the circuit developement work in this quarter was focused on the testing of MSI/LSI circuits (250-500 gates), and on the design of an LSI circuit (1000 gates). The preliminary data from the MSI/LSI circuits (from mask set AR4) are promising. Although the 5X5 but parallel multiplier (260 gates) did not operate completely and did not function at its predicted speed, the test data indicate that it can meet the design expectations when a mask error (a missing connection on 16 gates) is corrected. The 2 X 32 stage shift register (550 gates) has functioned up to 33 stages involving approximately 300 gates. Further testing is scheduled. An 8 X 8 bit parallel multiplier (1008 gates) has been designed, layed out, and the mask set containing this circuit is being fabricated. Keywords: Semi insulating, Ion implantation, Integrated circuits, High speed logic, Gallium arsenides.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jun 01, 1980
- Accession Number
- ADA186884
Entities
People
- C. G. Kirkpatrick
- F. H. Eisen
- F. S. Lee
- R. Zucca
- S. I. Long