RELIC: A Reliability Simulator for Integrated Circuits,

Abstract

Many of the failure mechanisms which cause reliability problems in VLSI chips can be influenced or avoided in the circuit design phase. RELIC is a reliability simulator developed to analyze and predict the stress and wear on MOS VLSI chips due to such mechanisms. RELIC uses a simple methodology for abstracting the idea of the stress from any particular failure mechanism, thus allowing analyses of many different failure mechanisms. There are currently three failure mechanisms analyzed by RELIC: metal migration, hot-electron trapping, and time-dependent dielectric breakdown (TDDB).

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Document Details

Document Type
Technical Report
Publication Date
Jan 01, 1987
Accession Number
ADA187493

Entities

People

  • Lance A. Glasser
  • Teresa S. Hohol

Organizations

  • Massachusetts Institute of Technology

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Circuits
  • Computer Science
  • Computer-Aided Design
  • Computers
  • Electrical Engineering
  • Electronics
  • Electrons
  • Engineering
  • Failure Mode And Effect Analysis
  • High Reliability
  • Integrated Circuits
  • Migration
  • Probability
  • Random Variables
  • Reliability
  • Simulations
  • Simulators

Fields of Study

  • Engineering

Readers

  • Integrated Circuit Design and Technology.
  • Theoretical Analysis.

Technology Areas

  • Microelectronics
  • Microelectronics - Microelectromechanical Systems