Optical Symbolic Processor for Expert System Execution
Abstract
The goal of this program is to develop a concept for an optical computer architecture for symbolic computing by defining a computation model of a high level language, examining the possible devices for the ultimate construction of a processor, and by defining required optical operations. In the quarter we undertook a detailed evaluation of our optical architecture (SPARO) for combinator graph reduction. Since we had determined that the interconnection network was the bottleneck in the performance of the architecture, our focus was on the message throughput of the simple register-based network. We derived an accurate performance model for the equivalent bidirectional ring network and found that the net parallelism in the architecture was indeed restricted by the low message traffic in the network. When messages exhibit no locality, the throughput for a 1024 processor network is 27. With local messages, the maximum throughput for the same network is 27. All results were subsequently verified by limited to 8 simulations.
Document Details
- Document Type
- Technical Report
- Publication Date
- Aug 31, 1987
- Accession Number
- ADA187494
Entities
People
- Aloke Guha
- Matthew Derstine
- Subra Natarajan
Organizations
- Honeywell International, Inc.