Integrated Circuit Design. (Phase 2).

Abstract

This report is in response to a request to provide an analysis on the design of an ultra-low power integrated circuit which will perform digital filtering on voice bandwidth signals. This chip will contain a 1024-tap linear phase filter with programmable weights, operate at a sample rate of 8 kHz, and will consume a maximum of 7.2 mW power with a 3.6-volt power supply. This monolithic filter will contain: an 8-12 bit a/d internal processing clock oscillator, and the digital filter. This study only reports on the power requirements of the digital filter portion of the chip, although all portions must be considered in the overall power budget. Preliminary device count and die size estimates are presented. The work presented here is based on an earlier study performed by Hughes Research Laboratories (HRL) for NOSC.

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Document Details

Document Type
Technical Report
Publication Date
Jul 01, 1987
Accession Number
ADA189060

Entities

People

  • J. G. Nash

Organizations

  • HRL Laboratories

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Access Time
  • Capacitance
  • Capacitors
  • Circuits
  • Complementary Metal-Oxide Semiconductors
  • Department Of Defense
  • Digital Filters
  • Energy Consumption
  • Filters
  • Frequency
  • Frequency Response
  • Image Processing
  • Integrated Circuits
  • Inverters
  • Metal Oxide Semiconductors
  • Semiconductors
  • Simulations

Fields of Study

  • Engineering

Readers

  • Adaptive Control and Estimation with Uncertainty in Dynamic Systems.
  • Computer Science/Computer Engineering/Data Science/Digital Signal Processing.
  • Integrated Circuit Design and Technology.