Calculating Depletion Region Carrier Concentrations with Capacitance-Voltage Measurements and Etching.

Abstract

Methods were developed for finding the charge carrier concentrations within the initial depletion region of n-type semiconductors. These methods combine the capacitance-voltage (C-V) technique with the etching of layers from the semiconductor surface. After each etch, the depletion region is made to end at the same location within the semiconductor. This location is used as a common reference and is arbitrarily chosen at a distance deep below the original unetched surface. For each etch depth, the voltage which extends the depletion region to the common reference distance is found. The voltage drop from an etch depth to the deeper common reference distance is the same as it would be if the semiconductor was not etched. This voltage drop is the sum of the applied voltage and the built-in potential. The built-in potential depends on the barrier potential at the semiconductor surface and the concentration at the common reference distance.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1987
Accession Number
ADA189630

Entities

People

  • Gordon H. Gainer Jr

Organizations

  • Air Force Institute of Technology

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Accuracy
  • Air Force
  • Charge Carriers
  • Charge Density
  • Computational Science
  • Computer Programs
  • Conduction Bands
  • Crystal Structure
  • Crystals
  • Electric Fields
  • Energy Bands
  • Energy Levels
  • Fermi Levels
  • Field Effect Transistors
  • Ion Implantation
  • N Type Semiconductors
  • Semiconductors

Fields of Study

  • Materials science

Readers

  • Electrical Engineering
  • Electromagnetic Wave Scattering and Antenna Radiation Engineering
  • Thin Film Deposition Science.

Technology Areas

  • Microelectronics
  • Microelectronics - Graphene