Parallel Memory Addressing Using Coincident Optical Pulses,
Abstract
The common computer bus, shared memory, multiprocessors are the most widely used parallel processing architectures. Unfortunately, such systems suffer from a memory/bus bandwidth limitation problem. For the designer of a hybrid optical/electronic supercomputer, an immediate temptation is to replace the shared electronic bus with an optical analog of higher bandwidth. To make that replacement is only a partial solution. The true bottleneck in such systems is in the address decoding circuits of shared memory units. In this paper we propose a new memory structure which provides for parallel access in a multiprocessor environment. The proposed system has two advantages. First, it distributes the address decoding circuitry to each of the requesting units on a common bus, thus eliminating the bottleneck of centralized decoding of encoded memory addresses. Second, it allows for parallel fetches of memory data with a level of parallelism limited only by the ratios of optical to electronic bus bandwidths and the dimensionality of the memory array.
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 01, 1987
- Accession Number
- ADA189767
Entities
People
- Donald Chirulli
- Rami Melhem
- Steve Levitan
Organizations
- University of Pittsburgh