Design and Evaluation of Fault-Tolerant VLSI/WSI Processor Arrays.
Abstract
This document is the final report of work performed under the project entitled 'Design and Evaluation of Fault-Tolerant VLSI/WSI Processor Arrays' supported by the Innovative Science and Technology Office of the Strategic Defense Initiative Organization and administered through the Office of Naval Research under Contract No. 00014-85-k-0588. With the concurrence of Dr. Clifford Lau, the Scientific Officer for this project, this final report consists of reprints of publications reporting work performed under the project. In the attached list of publications, items 1, 2, 3 and 7 are papers where fault-tolerant systems for processor arrays are proposed and studied. Studies on algorithmic and software aspects relevant to systems are reported in items 4, 5, 6, 12 and 13. Research on hardware and reconfigurability issues for fault-tolerant processor arrays is reported in items 8, 9, 10 and 11.
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 31, 1987
- Accession Number
- ADA190910
Entities
People
- Jose A. Fortes
Organizations
- Purdue University