Architecture of the Systolic Linear Algebra Parallel Processor (SLAPP)

Abstract

This paper will present preliminary concepts for the design of a systolic array of processors specifically aimed at efficient implementation of a core set of matrix operations consisting of matrix multiplication, QRD, SVD and generalized SVD. The algorithms to be implemented will be discussed briefly. Concepts for efficient implementation of the algorithms will be presented along with future plans.

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Document Details

Document Type
Technical Report
Publication Date
Aug 01, 1986
Accession Number
ADA191770

Entities

People

  • J. J. Symanski

Tags

Communities of Interest

  • Engineered Resilient Systems
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Algebra
  • Algorithms
  • Computations
  • Computer Programming
  • Data Storage Systems
  • Engineering
  • Fault Tolerance
  • Linear Algebra
  • Military Research
  • Numbers
  • Parallel Processors
  • Program Management
  • Rotation
  • Signal Processing
  • Simulations
  • Square Roots
  • Time Signals

Fields of Study

  • Engineering

Readers

  • Computer Programming and Software Development.
  • Linear Algebra
  • Systems Analysis and Design